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Job Description for Memory Design :

Exp: 3 - 7yrs
Location: Bangalore

Job responsibility:
- To work on development of embedded memory compilers ( SRAM, ROM, RF).
- Architecture exploration and choosing one based on PPA requirements.
- Schematic design and simulations
- Margin and characterization simulations
- Critical path modeling and optimization
- Interface with layout team to define the floor plan and layout guidelines for schematics. layout review to get optimum design.
- Interface with char team to define measurement points needed for timing data generation.
- Running robustness checks on the compiler.  
- Running equivalence verification (ex: ESPCV)
- Experience/Skills  required : 
- 3+ years of experience in design of emJob responsibility: bedded memory compilers
- Understanding of memory architectures and the tradeoffs involved.
- Sound fundamentals in CMOS basics and custom CMOS Circuit design
- Good understanding of bitcell operation and different assist techniques required in advanced nodes.
- Familiar with complete memory design ie architecture definition, circuit design, physical design, timing char and - design kit development 
- Familiarity with EDA tools like cadence Virtuoso, spice simulators .
- Knowledge of scripting language like Perl,shell etc
- B.E. / B.Tech / M.E. / M.Tech

Job Description for Memory Compiler Design Lead:

Exp: 7 - 11yrs
Location: Bangalore

Job responsibility and skills required:

Compiler Lead will own the design and development activities of one memory compiler with a team of 4 to5 engineers
custom memories including: SRAM, Register File, ROM, single port memories & multiport memories

Job Requirements

Be/B.tech/M.tech with 7 tp 11 years of experience in memory compiler design and development
Experience in allthe activities of memory compiler development.
- bitcell analysis
- pdk analysis
- memroy architecture and micro-architecture design
- margin and characterization
- design validation and view validation
- leading the team to deliver high quality memory product.
- guide the design and layout activities.
- emir,extraction
- scripting in shell,perl
- verilog modeling
- expertise in activities planning and scheduling

Job Description for Memory Layout:

Exp: 3 - 7yrs
Location: Bangalore

Job responsibility and skills required:
- Memory leaf cell layout development
- Migration of layout from one tech node to another
- Block and top level integration
- Quality and timely delivery
- EM-IR, area intensive layouts, Quality checks (QC)
- Understanding of design rules for 90nm and below
- Understanding of design rules for 14ff and 16ff is a plus.
- Drive multiple projects and provide necessary technical guidance to the engineers
- Understanding of DFM and DFY
- Understanding of memory compiler architectures
- Good debugging skills
- Knowledge of scripting in PERL/Shell/TCL scripting etc
- Proficient with tools like Cadence Virtuoso, Calibre LVS and Calibre DRC

Job Description for Memory Compiler Layout Lead:

Exp: 7 - 11yrs
Location: Bangalore

Job responsibility and skills required:

Compiler Lead will own the design and development activities of one memory compiler with a team of 4 to5 engineers
custom memories including: SRAM, Register File, ROM, single port memories & multiport memories

Job Requirements

- Be/B.tech/M.tech with 7 tp 11 years of experience in memory compiler design and development
hands on Experience in layout for all nodes from 14nm till 130nm nodes.
- Experience in handling the team of 3 to 4 engineers and deliver the high quality layouts in tight schedules.
- expertise in setting up the source files for drc,lvs,emir,dfm,extraction, LEF.

 
 
 

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