Physical Implementation

Physical Implementation

Physical Implementation is a process of transforming circuit description into physical layout. It describes position of cells and routes interconnections between them.

Physical Implementation of a large SoC has become increasingly challenging in advance technology nodes. Meeting time-to-market is more critical than ever in an extremely competitive marketplace that requires minimum amount of iterations between design and silicon. As a consequence of these challenges, it is vital that the design flow is robust enough to incorporate Engineering-Change-Order (ECO) at a later stage of the project; pre or post manufacturing.

Our Team has expertise in:

  • Diagrammatical representation
  • Design Netlist (after synthesis)
  • Floorplanning
  • Partitioning
  • Placement
  • Clock-tree Synthesis (CTS)
  • Routing
  • Physical Verification
  • GDS II Generation
  • Multiple EDA Tools and Flows